The Receiver processor unit accepts the pulse to pulse data (like Frequency, Pulse width, Amplitude, Direction of Arrival, time of Arrival etc.) measured by an ESM receiver and converts them into a time synchronous 128 bit data organized as 32bits x 4words. This board forms the interface between the receiver processor output and ESM processor input. The 32 bit x 4word data is interfaced to a high speed fiber optic cable (using a parallel to serial data converter) for onward transmission to an ESM processor. The maximum shadow time for transmitting the data for one pulse is <200ns (excluding the length of the fiber optic cable).
FPGA: XILINX VIRTEX-5 FPGA with TWO IBM PPC440 cores.